ADSP-21060LCW-160
Material:
Product Features
- 40MHz (25ns instruction rate) SISD SHARC Core
- 120MFLOPs peak performance
- Code compatible with all SHARC processors
- Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math
- Glueless connection for scalable DSP multiprocessing
- 4Mbits of on-chip dual-ported SRAM
- Six Link Ports for point to point connectivity and array multiprocessing
- Two synchronous serial ports with independent transmit and receive functions
- 10 Channel DMA controller
- Host Processor Interface
