The
AMD Zynq UltraScale+ RFSoC is an adaptive system-on-chip (SoC) that integrates high-speed RF-sampling data converters and forward error correction directly into an
UltraScale+ FPGA and ARM processing architecture.
Key Architecture Features
- Direct RF Sampling: Integrates multi-gigabit RF analog-to-digital (RF-ADCs) and digital-to-analog (RF-DACs) converters, eliminating external discrete conversion components.
- Processing System (PS): Features a 64-bit quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5F real-time processor.
- Programmable Logic (PL): UltraScale+ FPGA fabric combined with hardened soft-decision forward error-correction (SD-FEC) blocks for low-latency, high-throughput error decoding.
- Specialized Variants: Includes standard generations (Gen 1–3) and Digital Front-End (DFE) options optimized with hardened IP for wireless infrastructure like O-RAN and 5G.
- Wireless Communications: 5G massive MIMO, remote radio heads, and millimeter-wave IF transceivers.
- Aerospace & Defense: Phased-array radar, satellite communications, and military digital communications.
- Infrastructure: Cable access remote PHY nodes supporting DOCSIS 3.1 and
